motorola semiconductor technical data order number: MPC99J93/d rev 1, 08/2003 motorola timing solutions 1 product preview intelligent dynamic clock switch (idcs) pll clock driver the MPC99J93 is a pll clock driver designed specifically for redun- dant clock tree designs. the device receives two differential lvpecl clock signals from which it generates 5 new differential lvpecl clock outputs. two of the output pairs r egenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. features: ? fully integrated pll ? intelligent dynamic clock switch ? lvpecl clock outputs ? lvcmos control i/o ? 3.3v operation ? 32--lead lqfp packaging functional description the MPC99J93 intelligent dynamic clock switch (idcs) circuit continuously monitors both input clk signals. upon detection of a failure (clk stuck high or low for at least 1 period), the in p_bad for that clk will be latched (h). if that clk is the primary clock, the idcs will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. the typical phase bump caused by a failed clock is eliminated. (see applicatio n information section). figure 1. block diagram clk0 clk0 clk1 clk1 ext_fb ext_fb sel_clk dynamic switch logic pll pll_en 2 4 qb0 qb0 qb1 qb1 qb2 qb2 qa0 qa0 qa1 qa1 mr man_override clk_selected inp1bad inp0bad alarm_reset or 200 -- 360 mhz this document contains informatio n on a product under development. motorola reserves the ri ght to change or discontinue this product without notice . e motorola inc. 2003 MPC99J93 fa suffix 32--lead lqfp package case 873a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC99J93 motorola timing solutions 2 figure 2. 32--lead pinout (top view) gnd vcc qb0 qb0 qb1 qb1 qb2 qb2 vcc mr alarm_reset clk0 clk0 sel_clk clk1 clk1 gnd 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 MPC99J93 ext_fb ext_fb gnd clk_selected inp1bad inp0bad vcc pll_en man_override vcc_pll vcc qa0 qa0 qa1 qa1 table 1. pin descriptions pin name i/o pin definition clk0, clk0 clk1, clk1 lvpecl input lvpecl input differential pll clock reference (clk0 pulldown, clk0 pullup) differential pll clock reference (clk1 pulldown, clk1 pullup) ext_fb, ext_fb lvpecl input differential pll feedback clock (ext_fb pulldown, ext_fb pullup) qa0:1, qa0:1 lvpecl output differential 1x output pairs. connect one qax pair to ext_fb. qb0:2, qb0:2 lvpecl output differential 2x output pairs inp0bad lvcmos output indicates detection of a bad input reference c lock 0 with respect to the feedback signal. the output is active high and will remain high until the alarm reset is asserted inp1bad lvcmos output indicates detection of a bad input reference c lock 1 with respect to the feedback signal. the output is active high and will remain high until the alarm reset is asserted clk_selected lvcmos output ?0? if clock 0 is selected, ?1? if clock 1 is selected alarm_reset lvcmos input ?0? will reset the input bad flags and align clk_selec ted with sel_clk. the input is ?one--shotted? (50k ? pullup) sel_clk lvcmos input ?0? selects clk0, ?1? selects clk1 (50k ? pulldown) manual_override lvcmos input ?1? disables internal clock switch circuitry (50k ? pulldown) pll_en lvcmos input ?0? bypasses selected input reference around the phase--locked loop (50k ? pullup) mr lvcmos input ?0? resets the internal dividers forcing q outputs low. asynchronous to the clock (50k ? pullup) vcca power supply pll power supply vcc power supply digital power supply gnda power supply pll ground gnd power supply digital ground f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC99J93 motorola timing solutions 3 table 2. absolute maximum ratings a symbol characteristics min max unit condition v cc supply voltage -0.3 3.9 v v in dc input voltage -0.3 v cc +0.3 v v out dc output voltage -0.3 v cc +0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature -65 125 c a. absolute maximum continuous ratings are those maximum values bey ond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operatio n at absolute-maximum-rated conditions is not implied. table 3. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc -2 v mm esd protection (machine model) 175 v hbm esd protection (human body model) 1500 v cdm esd protection (charged device model 1000 v lu latch-up immunity 100 ma c in input capacitance 4.0 pf inputs ja thermal resistance junction to ambient jesd 51-3, single layer test board jesd 51-6, 2s2p multilayer test board 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 c/w c/w c/w c/w c/w c/w c/w c/w c/w c/w natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min jc thermal resistance junction to case 23.0 26.3 c/w mil-spec 883e method 1012.1 t j operating junction temperature a (continuous operation) mtbf = 9.1 years 110 c a. operating junction temperature impacts device life time. maximu m continuous operating junction temperature should be selected according to the application life time requirements (see application note an 1545 for more information). the device ac and dc parameters are speci- fied up to 110 c junction temperature allowing the MPC99J93 to be used in app lications requiring industrial temperature range. it is recom- mended that users of the MPC99J93 employ thermal modeling analysis to a ssist in applying the junction temper ature specifications to their particular application. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC99J93 motorola timing solutions 4 table 4. dc characteristics (v cc =3.3v 5%, t a =--40 to +85 c) symbol characteristics min typ max unit condition lvcmos control inputs (mr , pll_en, sel_clk, man_override, alarm_reset ) v ih input high voltage 2.0 v cc +0.3 v v il input low voltage 0.8 v i in input current a 100 a v in =v cc or gnd lvcmos control outputs (clk_selected, inp0bad, inp1bad) v oh output high voltage 2.0 v i oh =-24 ma v ol output low voltage 0.55 v i ol =24ma lvpecl clock inputs (clk0, clk1, ext_fb) b v pp dc differential input voltage c 0.1 1.3 v differential operation v cmr differential cross point voltage d v cc -1.8 v cc -0.3 v differential operation i in input current a 100 a v in =v cc or gnd lvpecl clock outputs (qa[1:0], qb[2:0]) v oh output high voltage v cc -1.20 v cc -0.95 v cc -0.70 v termination 50 ? to v tt v ol output low voltage v cc -1.90 v cc -1.75 v cc -1.45 v termination 50 ? to v tt supply current i gnd maximum power supply current 180 ma gnd pins i cc_pll maximum pll supply current 15 ma v cc_pll pin a. inputs have internal pull-up/pull-down resistors affecting the input current. b. clock inputs driven by differential lvpecl compatible signals. c. v pp is the minimum differential input voltage swing required to maintain ac characteristics. d. v cmr (dc) is the crosspoint of the differential input signal. functi onal operation is obtained when the crosspoint is within the v cmr (dc) range and the input swing lies within the v pp (dc) specification. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC99J93 motorola timing solutions 5 table 5. ac characteristics (v cc =3.3v 5%, t a =--40 cto+85 c) a symbol characteristics min typ max unit condition f ref input reference frequency 4 feedback 50 90 mhz pll locked f vco vco frequency range b 4 feedback 200 360 mhz f max output frequency qa[1:0] qb[2:0] 50 100 90 180 mhz mhz pll locked f refdc reference input duty cycle 25 75 % t ( ? ) propagation delay spo, static phase offset c clk0, clk1 to any q -0.15 0.9 +0.17 1.8 ns ns pll_en=1 pll_en=0 v pp differential input voltage d (peak-to-peak) 0.25 1.3 v v cmr differential input crosspoint voltage e v cc -1.7 v cc -0.3 v t sk(o) output-to-output skew within qa[2:0] or qb[1:0] within device 50 80 ps ps ? per/cycle rate of change of period qa[1:0] f qb[2:0] f qa[1:0] g qb[2:0] g 20 10 200 100 50 25 400 200 ps ps ps ps dc output duty cycle 45 50 55 % t jit(cc) cycle-to-cycle jitter rms (1 ) 25 ps t lock maximum pll lock time 10 ms t r ,t f output rise/fall time 0.05 0.70 ns 20% to 80% a. ac characteristics apply for parallel output termination of 50 ? to v cc - 2v . b. the input reference frequency must match the vco lo ck range divided by the feedback divider ratio (fb): f ref =f vco fb. c. clk0,clk1toext_fb. d. v pp is the minimum differential input voltage swing required to maintain a c characteristics including spo and device-to-device skew. ap- plicable to clk0, clk1 and ext_fb. e. v cmr (ac) is the crosspoint of the differential input signal. norma l ac operation is obtained when the crosspoint is within the v cmr (ac) range and the input swing lies within the v pp (ac) specification. violation of v cmr (ac) or v pp (ac) impacts the spo, device and part-to- part skew. applicable to clk0, clk1 and ext_fb. f. specification holds for a clock switc h between two input signals (clk0, clk1) no greater than 400 ps out of phase. delta period change per cycle is averaged over the clock switch excursion. g. specification holds for a clock switch between two input signals (clk0, clk1) at any phase difference ( 180 _ ). delta period change per cycle is averaged over the clock switch excursion. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC99J93 motorola timing solutions 6 applications information the MPC99J93 is a dual clock pll with on--chip intelligent dynamic clock switch (idcs) circuitry. definitions primary clock: the input clk selected by sel_clk. secondary clock: the input clk not selected by sel_clk. pll reference signal: the clk selected as the pll refer- ence signal by sel_clk or idcs. (idcs can override sel_clk). status functions clk_selected: clk_selected (l) indicates clk0 is selected as the pll reference signal. clk_selected (h) indicates clk1 is selected as the pll reference signal. inp_bad: latched (h) when it?s clk is stuck (h) or (l) for at least one ext_fb period (pos to pos or neg to neg). cleared (l) on assertion of alarm_reset . control functions sel_clk: sel_clk (l) selects clk0 as the primary clock. sel_clk (h) selects clk1 as the primary clock. alarm_reset : asserted by a negative edge. generates a one--shot reset pulse that clears input_bad latches and clk_selected latch. pll_en: while (l), the pll reference signal is substituted for the vco output. mr : while (l), internal dividers are held in reset which holds all q outputs low. man override (h) (idcs is disabled, pll functions normally). pll reference signal (as indicated by clk_selected) will always be the clk selected by sel_clk. the status function inp_bad is active in man override (h) and (l). man override (l) (idcs is enabled, pll functions enhanced). the first clk to fail will latch it?s inp_bad (h) status flag and select the other input as the clk_selected for the pll reference clock. once latched, the clk_selected and inp_bad remain latched until assertion of alarm_reset which clears all latches (inp_bads are cleared and clk_selected = sel_clk). note: if both clks are bad when alarm_reset is asserted, both inp_bads will be latched (h) after one ext_fb period and clk_selected will be latched (l) indicating clk0 is the pll reference signal. while neither inp_bad is latched (h), the clk_selected can be freely changed with sel_clk. whenever a clk switch occurs, (manually or by idcs), following the next negative edge of the newly selected pll reference si gnal, the next positive edge pair of ext_fb and the newly selected pll reference signal will slew to alignment. to calculate the overall uncertainty between the input clks and the outputs from multiple MPC99J93?s, the following procedure should be used. assuming that the input clks to all mpc9993?s are exactly in phase, the total uncertainty will be the sum of the static phase offset, max i/o jitter, and output to output skew. during a dynamic switch, the output phase between two devices may be increased for a short period of time. if the two input clks are 400ps out of phase, a dynamic switch of an MPC99J93 will result in an instantaneous phase change of 400ps to the pll reference signal without a corresponding change in the output phase (due to the limited response of the pll). as a result, the i/o phase of a device, undergoing this switch, will initially be 400ps and diminish as the pll slews to its new phase alignment. this transient timing issue should be considered when analyzing the overall skew budget of a system. hot insertion and withdrawal in pecl applications, a powered up driver will experience a low impedance path through an MPC99J93 input to its powered down vcc pins. in this case, a 100 ohm series resistance should be used in front of the input pins to limit the driver current. the resistor will have minimal impact on the rise and fall times of the input signals. acquiring frequency lock 1. while the MPC99J93 is receiving a valid clk signal, assert man_override high. 2. the pll will phase and frequency lock within the specified lock time. 3. apply a high to low transition to alarm_reset to reset input bad flags. 4. de--assert man_override low to enable intelligent dynam- ic clock switch mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC99J93 motorola timing solutions 7 outline dimensions fa suffix plastic lqfp package case 873a--03 issue b 12 ref d1 d/2 e e1 1 8 9 17 25 32 f f e/2 detail g base c1 c b b1 metal section f--f e seating plane rr2 _ (s) l (l1) 0.25 gauge plane a2 a a1 detail ad detail ad d1/2 e1/2 e/2 4x d 7 a d b a--b 0.20 h 0.1 c (1) _ 8x a, b, d a--b m 0.20 d c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datums a, b, and d to be determined at datum plane h. 4. dimensions d and e to be determined at seating plane c. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed themaximumbdimensionbymorethan 0.08--mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion: 0.07--mm. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25--mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.1--mm and 0.25--mm from the lead tip. dim min max millimeters a a1 7.00 bsc a2 0.80 bsc b 9.00 bsc b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 d d1 e e e1 l l1 1.00 ref r1 0.08 0.20 r2 s 1 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0 . 0 8 -- -- -- 07 __ _ 9.00 bsc 7.00 bsc 0.50 0.70 0.20 ref d 4x a--b 0.20 c d 6 6 4 4 detail g pin 1 index c 32x 28x h 5 8 plating 3 rr1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC99J93 motorola timing solutions 8 information in this document is provided solely to enable system and softwar e implementers to use motorola products. there are no express or implied c opyright licenses granted hereunder to design or fabr icate any integrated circuits or integrated circuits based on th e information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola ma kes no warranty, representation or guarantee r egarding the suitability of its products for any particular purpose, nor does motoro la assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation cons equential or incidental damages. ?ty pical? parameters that may be provided in motorola data sheets and/or specific ations can and do vary in different applic ations and actual performance may vary ov er time. all operating parameters, inc luding ?typicals?, must be validated for each custome r application by customer?s tec hnical experts. motorola does not convey any license under its patent r ights nor the rights of others. motorola products are not desi gned, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or susta in life, or for any other application in which the failure of the motorola product could create a situation wh ere personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hol d motorola and its officers, employees, subsid iaries, affiliates, and distributors harmless agains t all claims, costs, damages , and expenses, and reasonabl e attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim a lleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the us patent and trademark o ffice. all other product or service names are the property of their respe ctive owners. motorola, inc. is an equal opportunity/affirmative action employer. e motorola inc. 2003 how to reach us: usa/europe/locations not listed : japan : motorola japan ltd.; sps, tec hnical information center, motorola literature distribution 3--20--1, minami--azabu, minato--ku, tokyo 106--8573, japan p.o. box 5405, denver, colorado 80217 81--3-- 3440--3569 1--800--521--6274 or 480--768--2130 asia/pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industria l estate, tai po, n.t., hong kong 852--26668334 home page : http://motorola.com/semiconductors MPC99J93/d ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
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